This paper proposes a post-processing method, aiming at reducing both self-correlation and bias of bit sequence for true random number generator (TRNG). The post-processing circuit consists of two parts, the input randomization part and the n-bit Von Neumann (VN) algorithm part, playing the role of decorrelation and debias respectively. Two types of input randomization circuit are proposed, improving the lag1 correlation tolerance: from 0.009 to 0.02 for VN4W; from 0.1 to 0.14 for VN8W. The post-processing logic circuit is implied in 130 nm CMOS technology.