This work presents a 2.0-to-2.8GHz 653μW fractional-N all-digital phase-locked-loop (ADPLL) that achieves -242dB Figure of Merit (FoM) in 65nm CMOS for 2.4GHz ISM band applications. The best power-jitter trade-off is achieved at 981μW using a reference doubler with 535fs jitter and a -56dBc in-band fractional spur, which corresponds to a FOM of -246dB. The proposed 10-bit isolated constant-slope digital-to-time converter (DTC) with a power consumption less than 150μW and an INL of 0.15%. This ADPLL breaks the -240dB FoM barrier of sub-mW fractional-N ADPLLs.