This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65nm CMOS. By co-designing analog timing generation blocks and digital calibration algorithms, a high performance PLL is realized. The PLL achieves RMS jitter of 1.2ps and 0.3ps at 971MHz and 1 GHz in fractional-N mode and integer-N mode, respectively. The power consumption is 2.5mW and 2.2mW, corresponding to an FoM of -234.4dB and -246.7dB. The FoM in fractional-N mdoe is 10dB better than the previous best synthesizable design, while the fractional-N spur of -58.5dBc is comparable to custom designed PLLs.