Header
ポスターセッション発表概要
Implementation of Speed Limit Traffic Sign Recognition System on Rapid Prototyping Platform
○Anh-Tuan Hoang,小出 哲士,岡本 拓巳(広島大学)
This presentation describes a simple yet effective speed traffic sign recognition system implementation on FPGA. It is independent with color, and so robust under various conditions, such as daytime and night. The proposed system matches the processing speed requirement of over 15 fps and achieves over 98% in accuracy. The prototype system is implemented on Cadence Rapid Prototyping Platform for verification.
《ポスターセッション一覧》