This presentation is about a low-resource low-latency hybrid adaptive COordinate Rotation DIgital Computer (HA-CORDIC) hardware design. It is implemented both in FPGA and 180-nm CMOS technology. The adaptive algorithm reduces around 50% of iterations in comparison with the conventional CORDIC algorithm. The hybrid architecture together with resource sharing, parallel and pipeline processing are utilized in HA-CORDIC implementation. In CMOS implementation, the hardware architecture costs 10,299 cells with 0.41 mm2 area and fully operates at 50-MHz frequency.