This study uses Stochastic Resonance effect to build logic gates. These gates generate basic logic functions, where noise is fundamental to recover logic operations in the presence of mismatches. This approach offers three main advantages: low-power consumption, mismatch-tolerant design and a stable output. Since the response depends on stochastic processes, asynchronous circuits are a suitable application to design VLSI-circuits based on SR-logic gates. We demonstrate the performance of a dual-rail asynchronous pipeline through SPICE simulations for a 0.18-µm CMOS technology.