電子情報通信学会ソサイエティ大会講演要旨
C-12-28
Loop Latency Compensation Technique for Wide Loop Bandwidth ADPLL
○Hanli Liu・Kenichi Okada(Tokyo Tech)
This work presents a loop latency compensation technique for realizing the wide loop bandwidth (LBW) ADPLL. The latency is minimized to less than 0.25 reference period. In the measurement, a 5.5MHz LBW ADPLL is realized with 52MHz reference clock.