電子情報通信学会ソサイエティ大会講演要旨
C-12-27
A 1.2 ps-Jitter Fully-Synthesizable DTC-based Fractional-N Injection-Locked PLL using True Arbitrary Nonlinearity Calibration
○Bangan Liu・Huy Cu Ngo・Wei Deng・Yuncheng Zhang・Junjun Qiu・Kengo Nakata・Teruki Someya・Atsushi Shirane・Kenichi Okada(Tokyo Tech)
This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65nm CMOS. A true arbitrary non-linearity calibration scheme is specifically proposed for synthesizable DTC, together with an extensive digital calibration of the PLL. The RMS jitter of 1.2ps and 0.3ps is achieved at 1GHz output for fractional-N and integer-N operation, respectively. The power consumption is 2.5mW and 2.2mW, corresponding to an FoM of -234.4dB and -246.7dB.