電子情報通信学会ソサイエティ大会講演要旨
C-12-25
A High-Power-Efficiency Stacked PA and VCO Cell
◎Haosheng Zhang・Ashbir Aviat Fadila・Atsushi Shirane・Kenichi Okada(Tokyo Tech)
A stacked PA and VCO for the application of chip-scale-atomic-clock is proposed and designed. The architecture displays an improved power efficiency. The degradation of phase noise of VCO caused by the reduced DC supply is compensated by circuit design. Common source PA is adopted here instead of common gate PA to mitigate the degradation of phase noise of VCO by the cascode PA. It achieves phase noise of -120dBc/Hz at 1MHz frequency offset with maximum output power of 2.9dBm, while only consuming 12.2mW. The maximum power efficiency of 16%.