電子情報通信学会ソサイエティ大会講演要旨
A-20-8
Implementation of Paillier Cryptographic Circuit with High Radix Arithmetic Unit
◎Chun Cai・Hiromitsu Awano・Makoto Ikeda(The Univ. of Tokyo)
In this research, we specifically focus on the ASIC implementation of the Paillier cryptosystem using a parallelized high-radix arithmetic units and evaluated its performance from the aspects of circuit area and speed.The result shows the fastest radix-256 Paillier circuit synthesized consumes 20.72 ms of time which is about 5 times as fast as the previous research, with an area of 2308 kGate.